1. Field of the Invention
The present invention generally relates to electrically reprogrammable nonvolatile memory devices and methods of utilizing the same. More particularly, the invention relates to processes and structures for programming erasable programmable read-only memories (EEPROMs).
2. Description of the Related Art
Memory devices such as erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), or flash erasable programmable read-only memories (FEPROMs) are erasable and reusable memory cells which are often used in digital cellular phones, digital cameras, LAN switches, cards for notebook computers, etc. A memory cell operates by storing electric charge (representing either a binary “1” or “0” state of one data bit) on an electrically isolated floating gate, which is incorporated into a transistor. This stored charge affects the threshold voltage (VT) of the transistor, thereby providing a way to read the memory element. It is therefore crucial that the memory cell be able to maintain the stored charge over time, so that charge leakage does not cause data errors by converting the data bit from one binary state to another.
A memory cell typically consists of a transistor, a floating gate, and a control gate above the floating gate in a stacked gate structure. The floating gate, typically composed of polycrystalline silicon (i.e., “polysilicon”), is electrically isolated from the underlying semiconductor substrate by a thin dielectric layer, which is typically formed of an insulating oxide, and more particularly, silicon oxide. This dielectric layer is often referred to as a “tunnel oxide” layer, and is typically approximately 100 Å thick. Properties of the tunnel oxide layer must be strictly controlled to ensure the ability to read and write by transferring electrons across the tunnel oxide layer, while avoiding data loss through charge trapping or leakage. The control gate is positioned above the floating gate, and is electrically isolated from the floating gate by a storage dielectric layer, such as oxide-nitride-oxide (ONO). Electrical access to the floating gate is therefore only through capacitors.
A programmed memory cell has its VT increased by increasing the amount of negative charge stored on the floating gate, i.e., for given source and drain voltages, the control gate voltage which allows a current to flow between the source and the drain of a programmed memory cell is higher than that of a non-programmed memory cell. Therefore, the state of a memory cell is read by applying a control gate voltage below the predetermined level corresponding to the programmed state, but sufficiently high to allow a current between the source and the drain in a non-programmed memory cell. If a current is detected, then the memory cell is read to be not programmed.
One method to erase a memory cell (i.e., return the cell to its non-programmed state) is by exposing the floating gate to ultraviolet light, which excites the stored electrons out of the floating gate. The erasure of an EEPROM or FEPROM cell can also be accomplished via Fowler-Nordheim tunneling of charge from the floating gate, across the tunnel oxide, to the substrate, thereby reducing the stored charge in the floating gate. Under this mechanism for discharging the floating gate, for example, a large negative voltage (e.g., −10 V) is applied to the control gate, and a positive voltage (e.g., 5–6 V) is applied to the source while the drain is left floating. Electrons then tunnel from the floating gate through the tunnel oxide, and are accelerated into the source.
In an attempt to increase the storage density of an array of memory cells, efforts have been made to utilize multilevel memory cells, which are capable of representing more than two states by specifying more than one predetermined VT level. In such multilevel memory cells, each range of levels defined by the predetermined VT levels corresponds to a separate state. Therefore, to reliably distinguish between the various states, the multilevel memory cells must be programmed with narrow VT distributions within the ranges defined by the predetermined VT levels. Traditionally, these narrow VT distributions have been achieved using short programming pulses interleaved with verification read pulses in order to closely monitor the programmed level of a given cell. Examples of such multilevel memory cell programming are disclosed by Kucera, et al., U.S. Pat. No. 6,091,631; Fazio, et al., U.S. Pat. No. 5,892,710; and Harari, U.S. Pat. No. 5,293,560.
Such use of verification steps has two potential drawbacks. First, the circuitry needed to confirm that a particular cell has been properly programmed takes up valuable space on the semiconductor die. Second, the frequent verification steps take a substantial amount of time, thereby prolonging the programming process.